A computer system may include a PCI Express (PCIe) host bridge able to connect between devices, for example, between a processor and other units such as a graphics card, a memory unit, and the like. PCIe is an Input/Output (I/O) protocol allowing transfer of packetized data over high-speed serial interconnects with credit-based flow control. PCIe communication utilizes a layered protocol and includes a physical layer (to provide a link between devices), a data link layer (to provide packet sequencing, data protection, and acknowledgement signals), and a transaction layer. At the transaction layer, a PCIe Transaction Layer Packet (TLP) may include a packet header, a data payload, and an optional packet digest which may include End-to-End Cyclic Redundancy Check (ECRC) information, and which is included under the header credit for flow control.
Unfortunately, PCIe packets having a small data payload may result in significant link overhead. For example, PCIe packets having a small data payload consume both header credits and data credits without fully utilizing the data credit, thereby contributing to the link overhead.